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RF test structures with a limited metallization stack for evaluation of the upcoming 10 nm FD-SOI technology

Zhang Fu, Yinyin
(2024)

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ZhangFu_53571900_2024.pdf
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Details

Supervisors
Jean-Pierre Raskin
Faculty
Ecole polytechnique de Louvain
Degree label
Master [120] : ingénieur civil électricien, à finalité spécialisée
Abstract
The European Chip Act and France 2030 plan invested in the development of a new generation of Fully-Depleted-Silicon-on-Insulator (FD-SOI), aiming to go to 10-nm node and beyond. This work takes place in the context of the NextGen project. CEA is actively working on it, along with other industrial and academic organisations. This work focuses on RF test structures, more specifically, analytical and EM simulation tools that can help backup design choices in the conceptualization of RF test structures for a first FD10 test mask.