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Expanding SMAesH : implementing masked AES-256 encryption and decryption on shared 32-bits hardware

Bauffe, Vincent
(2024)

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Bauffe_10441900_2024.pdf
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Details

Supervisors
Standaert, François-Xavier
Faculty
Ecole polytechnique de Louvain
Degree label
Master [120] : ingénieur civil électromécanicien, à finalité spécialisée: mécatronique
Abstract
Hardware implementations of AES are subject to side-channel attacks. An efficient counter measure is masking of sensible data. In this work, we use the Hardware Private Circuit (HPC) masking scheme [CGLS21]. This method introduces sequential latency in otherwise combinatorial circuits. The design of masked hardware implementation is not straightforward. With the help of tools and concepts developed in [MCS22, CGM+23, KM22], we improve the masked 32 bits AES-128 implementation introduced in [MCS22]. The ability to decrypt a message is added, and the key size is increased to 256 bits. We evaluate the performance of this AES-256 and compare it to previous iterations. We also ensure it is still secure in the HPC masking scheme and compare two representations of the AES S-box [BP12, Can05].