Hardware-Trojans : attacks implementations against (un)-protected block cipher designs

Details

Supervisors

Standaert, François-Xavier

Faculty

Ecole polytechnique de Louvain

Degree label

Master [120] : ingénieur civil électricien

Abstract

Thanks to Snowden revelations, a societal awareness about security issues has emerged simulta- neously with the exponential number of connected electronic devices (i.e. IoT). This need for security is generally answered by designers based on well known mathematical descriptions of cryptographic algorithms. However, their practical hardware implementations may be exposed to security failures considering physical attacks. As an example, due to the globalization of ICs devices design, the threat of untrusted manufacturers involved in the fabrication process has emerged. This ultimate physical attack is known as hardware Trojan and can expose ICs to huge security failures. In this work, the practical of hardware Trojan exploiting side-channel/physical behavior of electronic devices is explored. First, it presents in details a parametric Trojan implementation based on timing violation and inducing faults in a pipelined AES block cipher architecture. Based on it, it describes secret key recovery methods using classical differential fault analysis and discuss the trade off encountered using the proposed strategy. Second, it presents in details a side-channel Trojan implementation, targeting protected AES and MOE block cipher implementation using the Trojan resilient framework proposed at CCS 2016 by Dziembowski et. al. Again, a key recovery strategy is described and discussions about the different trade off encountered and potential ameliorations are provided.