Hardware implementation of unlimited sampling for the analog-to-digital conversion of high dynamic range signals

Details

Supervisors

Flandre, Denis ; Feuillen, Thomas

Faculty

Ecole polytechnique de Louvain

Degree label

Master [120] : ingénieur civil électricien, à finalité spécialisée

Abstract

An essential component in systems capturing and processing analog signals is the Analog-to-Digital Converter (ADC). Whenever the signal amplitude exceeds the maximum recordable voltage from the ADC, it saturates, thus leading to a significant information loss. Recently, a novel system's architecture has been proposed to mitigate this issue, i.e. the so-called Modulo-ADC, using the modulo operation to fold the signal each time its dynamic range threshold is reached. The Unlimited Sampling theory can then be used to recover the initial signal from the modulo information. This type of ADC leverages the inherent modulo property of the phase by using a Voltage-Controlled Ring Oscillator (VCRO) as its core element. It allows to operate both modulo and quantization steps simultaneously. In this document, the blocks of the proposed VCRO-based Modulo-ADC system's architecture are presented. Then, the specifications and goal performance are defined based on the literature and on mathematical models. The targeted performance includes a sampling frequency of 1 MHz and achieving 100 folds on the input signal while minimizing the error at the modulo output, as quantified by a proposed index, i.e. the Number of Inverters Missed (NIM). To meet these objectives, three VCRO topologies are reviewed. The topology that best meets the specifications is selected for a further detailed design. Specifically, a sizing optimization of the chosen Back-Biased Ring Oscillator (BBRO) is carried out to achieve the desired performance. At the end, the BBRO simulations show satisfactory results, considering no errors w.r.t. the modulo information. However, to meet the specifications, the sampling frequency had to be adjusted to 0.1MHz, allowing for a theoretical achievement of 10 folds on the input signal, based on schematic simulations.

Citations

• APA

Weemaels, J. (2025). Hardware implementation of unlimited sampling for the analog-to-digital conversion of high dynamic range signals.