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vanderRest_31381800_2023.pdf
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- Abstract
- To immerse the user, Virtual Reality requires a low end-to-end system latency. To this end, latency compensation techniques are now a ubiquitous part of the VR pipeline. These usually consist of a last-minute transformation right before the image is displayed on screen. Despite their simplicity, these techniques greatly contribute to the user experience. However, new wireless VR headsets put additional constraints on the system by inserting an additional step of video compression and transmission over the network. To this end, we propose to embed the latency compensation algorithm on the head-mounted display, as a pre-processing step of the decoded image. We demonstrate in this work that this has numerous advantages, especially with image compression techniques such as JPEG-XS which are required to reduce the bitrate. We designed a lightweight embedded algorithm which transforms the received frame as it is being decoded, for minimal latency and memory requirements. This implementation targets FPGA devices, fitting on a Kintex KU035 FPGA device, with some headroom for a JPEG-XS decoder. The implementation was compared to a software reference running on a graphics card. It achieves good image quality with a fixed latency of 65 lines.